Dynamic Partial Self Reconfiguration

This book presents an approach (called OSSS+R) that eases the design of dynamic partial reconfigurable systems based on off-the-shelf FPGAs.

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Author: Andreas Schallenberg

Publisher: Sudwestdeutscher Verlag Fur Hochschulschriften AG

ISBN: 3838122631

Category:

Page: 232

View: 800

This book presents an approach (called OSSS+R) that eases the design of dynamic partial reconfigurable systems based on off-the-shelf FPGAs. An object oriented system description library is extended to allow modeling of such adaptive systems. Reconfigurable hardware is described by means of polymorphism and the concept of virtual hardware. The focus is on quick modeling and flexibility rather than in maximizing the grades of freedom for the design. The models can be simulated to perform functional validation by using a simulation library that is based on SystemC and C/C++. OSSS+R can be automatically synthesized to a RTL model. For demonstration purposes, parts of the transformation are implemented in a tool called Fossy. The generated models are cycle accurate with the original OSSS+R model. The feasibility of the proposed approach is demonstrated by implementing a design as a C++ model and then performing all proposed steps. Finally, the model was implemented on a FPGA prototyping platform.

Dynamic Partial Self reconfiguration

This thesis presents an approach (called OSSS+R) that eases the design of dynamic partial reconfigurable systems based on off-the-shelf FPGAs.

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Author: Andreas Schallenberg

Publisher:

ISBN: OCLC:1184320326

Category:

Page:

View: 667

This thesis presents an approach (called OSSS+R) that eases the design of dynamic partial reconfigurable systems based on off-the-shelf FPGAs. An object oriented system description library is extended to allow modeling of such adaptive systems. Reconfigurable hardware is described by means of polymorphism and the concept of virtual hardware. The focus is on quick modeling and flexibility rather than in maximizing the grades of freedom for the design. The models can be simulated to perform functional validation by using a simulation library that is based on SystemC and C/C++. OSSS+R can be automatically synthesized to a RTL model. For demonstration purposes, parts of the transformation are implemented in a tool called Fossy. The generated models are cycle accurate with the original OSSS+R model. The feasibility of the proposed approach was demonstrated by implementing a design as a C++ model and then performing all proposed steps. Finally, the model was implemented on a FPGA prototyping platform. engl.

FPGAs and Parallel Architectures for Aerospace Applications

Xcell J 79:44–49 Claus C,Muller FH, Zeppenfeld J, Stechele W (2007) Anew
framework toaccelerate Virtex-II Pro dynamic partial self-reconfiguration. In:
Proceedings of the IEEE international parallel and distributed processing
symposium, ...

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Author: Fernanda Kastensmidt

Publisher: Springer

ISBN: 9783319143521

Category: Technology & Engineering

Page: 325

View: 996

This book introduces the concepts of soft errors in FPGAs, as well as the motivation for using commercial, off-the-shelf (COTS) FPGAs in mission-critical and remote applications, such as aerospace. The authors describe the effects of radiation in FPGAs, present a large set of soft-error mitigation techniques that can be applied in these circuits, as well as methods for qualifying these circuits under radiation. Coverage includes radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.

Field Programmable Logic and Applications

It also provides support for relocatable partial bitstreams. The presented self-
reconfiguring platform enables embedded applications to take advantage of
dynamic partial reconfiguration without requiring external circuitry. 1 Introduction
This ...

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Author: Peter Y.K. Cheung

Publisher: Springer

ISBN: 9783540452348

Category: Computers

Page: 1182

View: 131

This book contains the papers presented at the 13th International Workshop on Field Programmable Logic and Applications (FPL) held on September 1–3, 2003. The conference was hosted by the Institute for Systems and Computer Engineering-Research and Development of Lisbon (INESC-ID) and the Depa- ment of Electrical and Computer Engineering of the IST-Technical University of Lisbon, Portugal. The FPL series of conferences was founded in 1991 at Oxford University (UK), and has been held annually since: in Oxford (3 times), Vienna, Prague, Darmstadt,London,Tallinn,Glasgow,Villach,BelfastandMontpellier.Itbrings together academic researchers, industrial experts, users and newcomers in an - formal,welcomingatmospherethatencouragesproductiveexchangeofideasand knowledge between delegates. Exciting advances in ?eld programmable logic show no sign of slowing down. New grounds have been broken in architectures, design techniques, run-time - con?guration, and applications of ?eld programmable devices in several di?erent areas. Many of these innovations are reported in this volume. The size of FPL conferences has grown signi?cantly over the years. FPL in 2002 saw 214 papers submitted, representing an increase of 83% when compared to the year before. The interest and support for FPL in the programmable logic community continued this year with 216 papers submitted. The technical p- gram was assembled from 90 selected regular papers and 56 posters, resulting in this volume of proceedings. The program also included three invited plenary keynote presentations from LSI Logic, Xilinx and Cadence, and three industrial tutorials from Altera, Mentor Graphics and Dafca.

Transactions on High Performance Embedded Architectures and Compilers IV

Ahmadinia, A., Bobda, C., Teich, J.: A dynamic scheduling and placement algo-
rithm for reconfigurable hardware. ... C., Müller, F.H., Zeppenfeld, J., Stechele, W.:
A new framework to accelerate Virtex-II pro dynamic partial self-reconfiguration.

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Author: Per Stenström

Publisher: Springer

ISBN: 9783642245688

Category: Computers

Page: 430

View: 205

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008.

Dynamically Reconfigurable Systems

18.3.1.2) it can be shown that fast dynamic reconfiguration can be applied in real-
time systems in order to save ... C., Miiller, F.H., Zeppenfeld, J., Stechele, W.: A
new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration.

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Author: Marco Platzner

Publisher: Springer Science & Business Media

ISBN: 9789048134854

Category: Technology & Engineering

Page: 441

View: 131

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.

Proceedings

Real - Time LUT - Based Network Topologies for Dynamic and Partial FPGA Self
- Reconfiguration Michael Huebner , Tobias Becker , Juergen Becker University
Karlsruhe ( TH ) , Germany http://www.itiv.uni-karlsruhe.de/ { huebner , beckert ...

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Author:

Publisher:

ISBN: UIUC:30112045657860

Category: Integrated circuits

Page:

View: 439

Header Parsing Logic in Network Switches Using Fine and Coarse grained Dynamic Reconfiguration Strategies

Current ASIC only designs which interface with a general purpose processor are fairly restricted as far as their ability to be upgraded after fabrication.

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Author: Alexander Sonek

Publisher:

ISBN: OCLC:892193097

Category:

Page:

View: 341

Current ASIC only designs which interface with a general purpose processor are fairly restricted as far as their ability to be upgraded after fabrication. The primary intent of the research documented in this thesis is to determine if the inclusion of FPGAs in existing ASIC designs can be considered as an option for alleviating this constraint by analyzing the performance of such a framework as a replacement for the parsing logic in a typical network switch. This thesis also covers an ancilliary goal of the research which is to compare the various methods used to reconfigure modern FPGAs, including the use of self initiated dynamic partial reconfiguration, in regards to the degree in which they interrupt the operation of the device in which an FPGA is embedded. This portion of the research is also conducted in the context of a network switch and focuses on the ability of the network switch to reconfigure itself dynamically when presented with a new type of network traffic.

Reconfigurable Computing for Video Coding

Video coding is widely used in our daily life.

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Author: Jian Huang

Publisher:

ISBN: OCLC:667235738

Category: Adaptive computing systems

Page: 95

View: 453

Video coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8x8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix. Compared to fixed hardware architecture using ASIC design approach, reconfigurable hardware design approach has higher flexibility, lower cost, and faster time-to-market. We propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture for DCT computations can compute different number of DCT coefficients in the zig-zag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose a configuration manager which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use LZSS algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams. The experimental results show that our approach can reduce the external memory accesses by 69% and can achieve 400 MBytes/s reconfiguration rate. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration. Prediction algorithm of zero quantized DCT (ZQDCT) to control the run-time reconfiguration of the proposed scalable architecture has been used, and 12 different modes of DCT computations including zonal coding, multi-block processing, and parallel-sequential stage modes are supported to reduce power consumptions, required hardware resources, and computation time with a small quality degradation. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration to meet the requirements set by the users.

SBCCI 2006

This work has discussed trade - offs and choices to implement dynamic self -
reconfigurable systems . ... It is recommended to use external static RAM to store
the partial bitstreams , since the controller to access these memories is very
simple ...

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Author:

Publisher: Association for Computing Machinery (ACM)

ISBN: STANFORD:36105131869740

Category: Electronic book

Page: 238

View: 972

Ninth International Workshop on Rapid System Prototyping

RIFLE-62 has a highly flexible architecture based around the Xilinx XC6200
family of dynamically reconfigurable FPGAs. ... in embedded DRL, reconfigurable
computing, but also other DRL applications, such as self-morphing and self-
reproduction automata. ... These, however, are not well suited for DRL
applications as they do not support partial configuration at device level and their
configuration is at ...

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Author: Jürgen Becker

Publisher: Institute of Electrical & Electronics Engineers(IEEE)

ISBN: UCSC:32106013999468

Category: Computers

Page: 226

View: 546

Reconfigurable System Design and Verification

Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, ...

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Author: Pao-Ann Hsiung

Publisher: CRC Press

ISBN: 9781351834926

Category: Computers

Page: 268

View: 980

Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text explains topics in such a way that they can be immediately grasped and put into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrating real-world applications, detailed explanations of complex algorithms, and self-explaining illustrations add depth to the presentation. Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, making it very difficult to search, compare, and select the technique most suitable. The authors do it all for you, making it easy to find the techniques that fit your system requirements, without having to surf the net or digital libraries to find the candidate techniques and compare them yourself.

SBCCI 2007

[ 2 ] N. Bergmann , J. Williams , “ Embedded Linux as a platform for dynamically
self - reconfiguring systems - on - chip ” . ... [ 15 ] M. Hübner , J. Becker , “
Exploiting Dynamic and Partial Reconfiguration for FPGAs – Toolflow ,
Architecture and ...

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Author: Antonio Petraglia

Publisher:

ISBN: STANFORD:36105133408695

Category: Electronic book

Page: 366

View: 283

FCCM 2004

[ 66 ] S. Singh , J. Hogg , and D. McAuley , “ Expressing Dynamic Reconfiguration
by Partial Evaluation , " in FCCM , April 1996 , pp . 188– 194 . [ 67 ] Q. Wang ... [
84 ] J. von Neumann , Theory of Self - Reproducing Automata . University of
Illinois ...

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Author: Jeffrey M. Arnold

Publisher: Institute of Electrical & Electronics Engineers(IEEE)

ISBN: 0769522300

Category: Computer engineering

Page: 346

View: 804

FCCM presents recent work on the use of reconfigurable logic as computing elements. The proceedings focuses on topics such as device architecture, system architecture, compilation and programming tools, run time environments, nano technology, and applications.

Computer Architecture 96

Dynamic reconfiguration takes the reprogrammability of FPGAs a step further by
allowing seamless reconfiguration during ... [ Saleeba , 1993 ; Van den Bout et al
, 1992 ; Athanas and Silverman , 1991 ; Athanas , 1992 ) Partial reconfiguration is
... A step beyond the idea of dynamic reconfiguration is " self reconfiguration ” .

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Author: Ronald Pose

Publisher: Springer

ISBN: PSU:000031279956

Category: Computers

Page: 225

View: 609

The Australasian Computer Architecture Workshop (ACAW) is a series of annual workshops which was originally developed for the computer architecture community. ACAW '96, the fourth in this series, was the first to be held as a full conference with refereed research papers solicited from authors in Australia, Japan and Austria. These proceedings are a result of this successful two-day event and contain 14 research papers covering various areas of computer architecture as well as the papers of the two keynote speakers.

Built In Self Test for Input Output Buffers

Programmable Input/Output (I/O) cells are an integral part of any Field Programmable Gate Array (FPGA).

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Author: Sudheer Vemula

Publisher: LAP Lambert Academic Publishing

ISBN: 384337015X

Category:

Page: 100

View: 188

Programmable Input/Output (I/O) cells are an integral part of any Field Programmable Gate Array (FPGA). The resources associated with the programmable I/O cells are increasing as newer architectures of FPGAs are being developed and this increases the importance of testing them. A general Built-In Self-Test (BIST) architecture to test the programmable I/O cells in FPGAs or associated with the FPGA core of System-on-Chip (SoC) implementations is proposed. The I/O cells are tested for various modes of operation along with their associated programmable routing resources. The proposed BIST architecture has been implemented and verified on Atmel AT94K10 and AT94K40 SoCs. A total of 161 and 303 configuration downloads are required to test the I/O cells of AT94K10 and AT94K40 devices, respectively. The use of an embedded processor for dynamic partial reconfiguration reduced the number of configuration downloads to three for both the AT94K10 and AT94K40 devices. The implementation of dynamic partial reconfiguration gave a speed up of 99.39 times in test time and a reduction in configuration memory storage requirements by 101 times for AT94K40 devices.

IEEE Workshop on FPGAs for Custom Computing Machines

A self - reconfiguring processor P . C . French R . W . Taylor Computer Systems
Engineering Group Department of ... For appropriately designed modules , this
implies that partial dynamic reconfiguration is , at least in theory possible ...

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Author: Duncan A. Buell

Publisher:

ISBN: 0818638907

Category: Computer architecture

Page: 212

View: 189

Proceedings of a symposium held in Napa, California in April 1993. Papers discuss fine grain parallelism on a MIMD machine using FPGAs, compiler and architecture of PRISM II, realizing massively concurrent systems of the SPACE machine, virtual computing, a self-reconfiguring processor, the Anyboard,

Reconfigurable Technology

The RTOS acts as a fully dynamic scheduler , assigning tasks to specific
processors only at run time . 5. ... We describe this specific vision task by self -
defined data - flow C - like language , compiling it and downloading the link - list
to ADSP21160's data memory . ... was supported partial by the Intelligence Robot
20 Proc .

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Author:

Publisher:

ISBN: UOM:39015049129193

Category: Computer architecture

Page:

View: 710